This invention generally relates to a semiconductor integrated circuit having low-power consumption circuits made of integrated injection logic (IIL) circuits.
The operating voltage of an IIL circuit is approximately 0.8 volt, which is lower than those of TTLs and ECLs, while the current flow per gate is small, and therefore, IIL circuits consume less power. Meanwhile, IIL circuits can be manufactured by the manufacturing process of bipolar transistors. Therefore, by combining IILs and bipolar transistors, both having less element area, on the same substrate, it is possible to increase the degree of integration density of a semiconductor integrated circuit.
Customary semiconductor elements having bipolar transistors are difficult to operate with a voltage of 0.8 volt. That is 5 volts is usually applied to TTLs, and 10 volts to linear ICs. Accordingly, an IC, in which customary bipolar transistors and IILs are combined, requires two different power supplies. However, since IILs are of a constant-circuit driven type, a voltage of 0.8 volt cannot be simply applied thereto. Namely, a current flowing through an IIL circuit has to be limited by connecting it to a low-voltage power source or by connecting a resistor in series thereto. In such a combined IC, it is a usual practice that the power source used for the bipolar transistors is used by connecting a resistor in series. In this case, most of the electrical power is consumed by the series resistor, and therefore, the advantage of low-power consumption by an IIL structure is cancelled.
In such a combined IC, the grounded or reference point of the IIL circuit included therein corresponds to the collectors of bipolar transistors, and therefore, the IIL circuit can be separated from the silicon substrate. Moreover, since the amount of current flowing into the grounded point does not vary in accordance with the switching condition of each IIL gate, the entire IIL circuit may be divided into a plurality of sections. Namely, a plurality of IIL circuits each including at least one IIL gate may be stacked in the form of multi-layer so that voltage efficiency may be increased. For instance, when the entire IIL circuit is divided into two, the divided IIL circuits may be stacked in such a manner that the injection input terminal of an IIL circuit is connected to the power source, and the ground point of this IIL circuit is connected to the injector input terminal of the other IIL circuit whose ground point is used as the ground point of the entire stacked circuit. With this arrangement, the total power consumption can be reduced by half because the total current flowing through the entire circuit is only one-half that of unstacked arrangement, while the current per each IIL gate is maintained the same. Additionally, if the entire IIL arrangement is further divided into different numbers of circuits, the total power consumed may be reduced to 1/3, 1/4 and so on.
In such a stacked IIL circuit configuration, there is a problem in connection with a circuit for transmitting a signal from the top or upper layer to the bottom or lower layer or vice versa. Namely, if shifting of the signal bias level were satisfactorily performed, the operation of the IIL circuit would be apt to be unstable and/or the delay time in signal transmission is apt to increase.
FIG. 1 shows an example of a conventional circuit arrangement of a stacked IIL circuit. This example is a q-stage ring oscillator, which is constructed of seven gate circuits 3 having an IIL structure including a first or bottom layer having three gates connected in parallel, a second or middle layer and a third or upper layer each having two gates connected in parallel, which threee layers are stacked to form a three-layer structure. In FIG. 1, the reference numerals 1-1 to 1-7 are npn transistors for switching respective IIL gates 3-1 to 3-7 numerals; 2-1 to 2-7 are pnp transistors functioning as active loads of respective IIL gates 3-1 to 3-7. Each of the IIL gates 3-1 to 3-7 is constructed of the transistors 1-1 and 2-1, 1-2 and 2-2 and so on. As described above, in the first layer, three gate circuits 3-1 to 3-3 are connected in parallel, while in each of the second and third layers, two gate circuits 3-4 and 3-5, 3-6 and 3-7 are connected in parallel. The references 4 and 5 are respectively a pnp transistor and an npn transistor for effecting level shifting of the signal to be transmitted from the third layer to the first layer, and each of the transistors 4 and 5 constitutes one stage of the 9-stage ring oscillator. The reference numerals 6 to 9 indicate common lines, and in this example, the common line 6 is at ground potential; the common line 7, approximately 0.8 volt; the common line 8, approximately 1.6 volt; and the common line 9, approximately 2.4 volt. The reference numeral 10 is a constant-current source.
In the conventional circuit of FIG. 1, the transmission of the signal from the left-most IIL gate 3-1 of the first layer to the left-most IIL gate of the second layer is effected by only connecting the collector of the npn transistor 1-1 of the first layer to the base of the transistor 1-4 of the second layer, and thus no level shifting is required. Signal transmission from the collector of the transistor 1-5 of the right-most IIL gate 3-5 of the second layer to the base of the transistor 1-6 of the left-most IIL gate 3-6 of the third layer is also effected in the same manner. In this circuit, it is to be noted that the base voltage of the transistor 1-4 of the second layer becomes ground potential when the transistor 1-1 of the first layer turns on. Accordingly, the voltage variation range at the base of the transistor 1-4 of the second layer is 1.6 volt because the voltage of 0.8 volt between the base and emitter of the transistor 1-4 of the second layer is added to the voltage of 0.8 volt at the common line 7 although the base voltage variation range in a singlelayer IIL arrangement is only 0.8 volt or so. In other words, when the IIL gates 3-1 to 3-7 are constructed in the form of a single layer, the base voltage of each of the transistors 1-1 to 1-7 varies between its emitter voltage, i.e. ground potential, and a base voltage (approximately 0.8 volt) in the on-state thereof. However, when the IIL circuit is divided into a plurality of sections, for instance, into two as described above, to be stacked in the form of two layers, the base voltage variation range in connection with the transistor 1-4 becomes approximately 1.6 volt. Therefore, it takes twice the interval required in a single-layer arrangement for the base voltage to be increased to 1.6 volt because the base voltage of the transistor 1-4 of the second layer rises by charging a parasitic capacitance between its base and collector or emitter after the transistor 1-1 of the first layer becomes on from an off-state. This is because the collector current of the transistor 2-4 of the second layer is constant, and therefore, the parasitic capacitance is charged at a constant rate.
Although operation has been described in connection with the transistor 1-4 of the second layer, the transistor 1-6 of the third layer operates in the same manner. Namely, the range of the voltage variation at the base of the transistor 1-6 in the third layer is as great as 2.4 volt or so, and accordingly the transistor 1-6 requires more time until it turns on.
In the circuit of FIG. 1, the signal to be transmitted from the third layer to the first layer cannot be satisfactorily transmitted without level shifting, and therefore, transistors 4 and 5 are added for effecting level shifting. In this example, the signal from the IIL gate 3-7 is once inverted by the transistor 4, and is further inverted by the transistor 5. Namely, the transistors 4 and 5 constitute a two-stage gate circuit whose structure is different from that of an IIL circuit, and the entire circuit arrangement of FIG. 1 functions as a 9-stage ring oscillator.
The problem in level shifting is that it takes a long period of time for the transistor 4 to turn off when the transistor 1-7 connected to the transistor 4 turns off. This is because the voltage at the base of the transistor 4 cannot rise rapidly because there is no path for charging the parasitic capacitance around the point A in the vicinity of the base of the transistor 4; namely, the voltage at the base thereof gradually rises as the parasitic capacitance is charged by a small current from the emitter of the transistor 4. Another problem is that it takes a long period of time for the transistor 5 to become off in a similar manner because there is no path for discharging the charge stored in the parasitic capacitance at the base side of the transistor 5.
For this reason, in the conventional stacked structure of logic circuits of FIG. 1, delay in signal transmission time increases at the above-mentioned level shifting portion. Therefore, when AND and/or OR gates are formed in IIL circuits, the input signals of these logic gates are apt to be difficult to synchronize with its clock pulse, causing these logic circuits to malfunction.